1. Field of the Invention
The present invention relates to a static semiconductor memory device and, more particularly, to a static semiconductor memory device, in which degradation of device quality or reduction of operational margin can be prevented.
2. Description of the Related Art
In an SRAM, dummy memory cells that cannot function as memory cells are arranged around the memory cells in order to reduce a defect rate of the memory cells due to a non-coincidence of the dimension of a pattern or an incorrect shape of the pattern after a lithography process through an abrupt change in device density. Naturally, the dummy memory cell induces the incorrect pattern shapes of polysilicon gates or contact holes due to a proximity effect, compared with the memory cell. As a consequence, the dummy memory cells are designed to be separated from the memory cells from the viewpoint of circuit logic, so as to avoid any adverse influence on a normal functional operation of the memory cells.
The dummy memory cell has a layout structure similar to that of the memory cell to keep the continuity of a layout. In particular, it is desired that the dummy memory cell has the arrangement or shapes of a well, a diffusion layer, a polysilicon gate, a contact hole, a metal wiring and a via-contact identical to or similar to those of the memory cell. As a consequence, the circuit configuration of the dummy memory cell is equivalent to that of the memory cell.
Japanese Laid Open Patent Application (JP-A-Showa 61-214559) discloses the arrangement of dummy memory cells around memory cells. In this first conventional example, the dummy memory cells without any operation are arranged in a boundary between a region where the memory cells are continuously arranged, and another region where the memory cells are not continuously arranged. Also, Japanese Laid Open Patent Application (JP-A-Heisei 7-176631) as a second conventional example discloses a technique for using a dummy transistor in a dummy memory cell as a pull-up transistor to keep a bit line at a predetermined voltage. Moreover, Japanese Laid Open Patent Application (JP-P2004-071118A) as a third conventional example discloses an SRAM, in which a voltage decrease rate of a dummy bit line is higher than that of a bit line. In this third conventional example, a P-channel MOS transistor for a load in a memory cell is replaced with an N-channel MOS transistor. Also, a power supply voltage is applied to a memory node, and a ground voltage GND is applied to a source of the N-channel MOS transistor. A current flows out on a line of the ground voltage from a dummy bit line when a word line is raised up to an “H” level, thereby improving the operational margin of the SRAM.
However, in the conventional SRAMs, since power is supplied to a dummy memory cell from a power supply voltage VDD, a leakage current flows in a normal dummy memory cell although it is slight. In addition, although the dummy memory cell is permitted to have an abnormal shape, an unexpected current possibly flows. Specifically, various defects could be considered such as a short-circuit between a source and a drain in a transistor due to defect of a polysilicon gate, a short-circuit between the source and the drain due to the excessive formation of a diffusion layer, a short-circuit between the power supply voltage and a substrate voltage due to the defect of a metal wiring. In the conventional examples, a memory cell, a dummy memory cell and a Tap cell share a power supply wiring and a ground wiring, and further, the same kind of well layers arranged adjacently in an X direction. In this case, an unexpected current path is generated, and a large amount of leakage current flows through the unexpected current path. As a result, the voltages of the power supply wiring and the ground wiring are temporarily fluctuated. Thus, the operational margin of the memory cell connected to the power supply wiring and the ground wiring is greatly influenced by the above-described fluctuation of the voltage. Additionally, in the conventional SRAM, the leakage current slightly flows even through a transistor of the dummy memory cell having the correct shape.
In recent years, a power supply voltage is reduced as the pattern of an LSI has become finer, so that an operation current, i.e., a dynamic current is reduced to achieve low power consumption. However, a leakage current on standby, i.e., a static current is not decreased more than that of the operation current. Thus, a ratio of the leakage current in the current consumption increases. When the voltage is more decreased and the gate length is more shortened, the decrease in leakage current has come to an end at a certain stage, and thereafter, the leakage current is increased in turn. This becomes prominent in a 90-nm generation and the subsequent generations, and various countermeasures are proposed to reduce the leakage current. For example, a system is configured such that a power supply voltage becomes zero on the standby. Similarly, the ratio of the leakage current in the current consumption is increased due to the miniaturization in the dummy memory cell with correct shapes or with few incorrect shapes. Furthermore, as the number of dummy memory cells increases, the total leakage current becomes more. As a consequence, the leakage current flowing in the dummy memory cells increases a total leakage current in the SRAM, to increase the power consumption.
The dummy memory cell does not have a mechanism for writing or reading data. Therefore, a test of the dummy memory cell is not carried out or cannot be carried out. However, it was found by the inventor of the present invention that such an influence of the leakage current in the dummy memory cells to a memory cell array could not be ignored in the SRAM in a 0.15-μm generation. The leakage current in the dummy memory cell causes an erroneous operation of the SRAM and the defective quality due to increase in current consumption or power consumption. In future, as the pattern of the LSI becomes finer, there would be a possibility of degradation of quality due to the leakage current generated in the dummy memory cell, that is, an unexpected leakage current due to an incorrect shape or a leakage current associated with the fineness of a circuit configuration, if the conventional configuration is kept.